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openbench_fgen

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what

A completely open design for a function/waveform generator: hardware, firmware, software

Notes & stuff

Waveform generation

Waveforms we want (in order of importance)

  • Sine wave
  • Square wave (with variable PWM)
  • Triangle wave
  • Sawtooth (possibly a modification of triangle wave???)
  • arbitrary waveform (sync, envelopes, etc)

Frequency range:

  • 1 Hz or lower
  • 100 KHz or higher (must cover audio ranges)
  • 1mHz → 10MHz is ideal (digital/analog ranges)

Generator tech

Two options for chip 'styles' is the all-in-one oscillator (ICL3038, etc) +PLL or DDS

Oscillators

All-in-one is nice, although not very stable w/o PLL. Two options available, MAX038 & XR220.

  • The MAX038 is completely unavailable.
  • And the XR2206 kinda sucks.

Pros: easy, cheap, simple Cons: unavailable, PLL required

DDS

Direct-Digital-Synthesis, currently popular. Basically: wavetable + 24 or 32 bit adder and sampling above nyquist to get precision waveforms.

  • Pros: digital, precise, no PLL needed
  • Cons: hard to get high frequencies because of oversampling

Either roll your own or buy off the shelf (basically from AD)

Off the shelf, AD parts

They come with sync out, very very high speeds. But only sine and square out, and in small packages (TSSOP).

Roll your own

Idea #1: Get a chunk of SRAM (like, say, CY7C1399B-12VXC), fill it with your wavetable, then clock it with a variable clock (LTC6903 1KHz→68MHz !!) maybe use along with adder/scaler to provide more range at high/low freq. We could get up to 4MHz, nice!

  • Pros: high frequency range
  • Cons: complex, lots of glue and fiddling, but might be a good solution

Idea #2: SRAM + 32 bit adder, just like AD. Maybe make the adder in a CPLD or something else that can be clocked super-fast (See ELM's DDS generator)

  • Pros: the ideal solution: high resolution, high speed
  • Cons: ugh CPLD, dont even know if there's a good solution available for the price/package we need, a little pricey

Look at: http://www.rotgradpsi.de/mc/fg/fg.html , a handmade adder

For CPLD, 100MHz PLCC (44 or 68) either XC9500 (xilinx) or MAX7000 (altera)

Idea #3: Hand-roll the adder code into an AVR microcontroller, and use onboard memory. Lots of examples: 9 Cycles of ASM w/LPM (note: can't we do this in 8 cycles by using LD? just make sure we have an AVR with more than 256b of RAM)

  • Pros: ultra-cheap/simple
  • Cons: 8 @ 20MHz → low frequency output (20M/16samples/8cycles = ~150KHz), 8bit resolution

Other possibilities include going with an SX instead of AVR: SX28 can be clocked up to 75MIPS (maybe give us 500KHz…but will draw an insane 100mA from 5V. jesus!)

/home/ladyada/public_html/wiki/data/attic/openbench_fgen.1176421581.txt.gz · Last modified: 2016/01/28 18:05 (external edit)