The LCD breakout has 6 bit x RGB output, which we can turn into a 6-bit DAC → RGB analog 0.7Vpp into 75 ohms use 278 & 556 ohm resistors for the R2R ladder, this will give you ~0.7v signal when plugged into a 75 ohm termination such as a monitor.
For the LCD, this is by default = 0x45000190
HW_LCDIF_VDCTRL2 = (96) « 24 | (640 + 16 + 96+ 48) = 0x60000320
For the LCD, this is by default = 0x0000011a (dec. 282)
so HW_LCDIF_VDCTRL1 = 524 (0x20C)
VSYNC_OEB = 0 (generate vsync) ENABLE_PRESENT = 0 (no enable necessary) 0x0 VSYNC_POL = 0 (negative sync!) HSYNC_POL = 0 (negative sync!) DOTCLK_POL = D/C ENABLE_POL = D/C 0x0 VSYNC_PERIOD_UNIT = 1 (count in lines) VSYNC_PULSE_WIDTH_UNIT = 1 (count in lines) 0x3 HALF_LINE = 0 HALF_LINE_MODE = 1 (no half line for vga, right?) 0x4 VSYNC_PULSE_WIDTH = 2 0x2
by default = 0x004b0027
By default, (32x0x240 LCD) = 0x00f00140
For 640x480 VGA it should be = 0x01E00280
So the main clock is 454 right?
To get a pixel clock of 25.175 MHz, 454 MHz / 18 → DIV = 0x12 CLKGATE = 0 DIV = 0x12 → CLK of 21 Mhz
Hmm, guess our chip isnt running at 454? Or is it our scope? Try 0x0F for 25MHz which matches with eveything else. Which means we're running at 375MHz?
PIXCLK = 0x0F
HSync = 31.3Khz (should be 31.46)
Vsync = 59.75 Hz (should be 60.04)
Vsync negative pulse = 63.9 uS (should be 63.57) (it is low from the negative edge of one HSync to another negative Hsync edge)
Hsync negative pulse = 3.83 uS (should be 3.81)
HSync Back porch = 5 uS (should be 1.9?), Hsync front porch = ~14.2uS (should be 0.9?)