chumbyhackerboard:vga
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chumbyhackerboard:vga [2010/09/21 05:02] ladyada |
chumbyhackerboard:vga [2016/01/28 18:05] (current) |
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| use 278 & 556 ohm resistors for the R2R ladder, this will give you ~0.7v signal when plugged into a 75 ohm termination such as a monitor. | use 278 & 556 ohm resistors for the R2R ladder, this will give you ~0.7v signal when plugged into a 75 ohm termination such as a monitor. | ||
| - | ====== VSync ====== | ||
| - | We want to get the Vsync to about 60hz | ||
| - | |||
| - | By default, the 'internal' LCD sync rate is 117 Hz | ||
| - | <code> | ||
| - | chumby-:/ # cat /proc/driver/chumbyfwfb/fb_stats | ||
| - | PXP frequency: 59 Hz | ||
| - | LCDIF frequency: 117 Hz | ||
| - | VSYNC Edge IRQs: 49077 | ||
| - | Cur Frame Done IRQs: 49224 | ||
| - | Missed PXP firings: 5 | ||
| - | </code> | ||
| - | |||
| - | This is set by the HW_CLKCTRL_PIX register | ||
| - | |||
| - | <code> | ||
| - | chumby-:/ # regutil -r HW_CLKCTRL_PIX | ||
| - | Value at 0x80040060: 0x0000001d | ||
| - | </code> | ||
| - | |||
| - | Lets divide the frequency by 2 which means multiplying the divider by two | ||
| - | |||
| - | <code> | ||
| - | chumby-:/ # regutil -w HW_CLKCTRL_PIX=0x38 | ||
| - | Setting 0x80040060: 0x0000000e -> 0x00000038 ok | ||
| - | </code> | ||
| - | |||
| - | <code> | ||
| - | chumby-:/ # cat /proc/driver/chumbyfwfb/fb_stats | ||
| - | PXP frequency: 32 Hz | ||
| - | LCDIF frequency: 62 Hz | ||
| - | VSYNC Edge IRQs: 69919 | ||
| - | Cur Frame Done IRQs: 70118 | ||
| - | Missed PXP firings: 5 | ||
| - | </code> | ||
| - | |||
| - | Actually, to get the closest to 60 Hz. I went with HW_CLKCTRL_PIX=0x37 (so says the tek 'scope) | ||
| - | |||
| - | How the Hsync is 17.08 KHz (we want 2x that 31.46 KHz) | ||
| - | |||
| - | |||
| - | THIS IS ALL WRONG. START OVER! | ||
| ====== Horizontal Sync HW_LCDIF_VDCTRL2====== | ====== Horizontal Sync HW_LCDIF_VDCTRL2====== | ||
| For the LCD, this is by default = 0x45000190 | For the LCD, this is by default = 0x45000190 | ||
| + | |||
| + | We want... | ||
| * Per horizontal line: 640 pixels | * Per horizontal line: 640 pixels | ||
| Line 59: | Line 19: | ||
| SO! | SO! | ||
| - | HW_LCDIF_VDCTRL2 = (96) << 24 | (640 + 16 + 48) = 0x600002C0 | + | HW_LCDIF_VDCTRL2 = (96) << 24 | (640 + 16 + 96+ 48) = 0x60000320 |
| ====== Vsync HW_LCDIF_VDCTRL1 ====== | ====== Vsync HW_LCDIF_VDCTRL1 ====== | ||
| For the LCD, this is by default = 0x0000011a (dec. 282) | For the LCD, this is by default = 0x0000011a (dec. 282) | ||
| + | |||
| + | We want... | ||
| * Per vertical line: 480 horizontal lines | * Per vertical line: 480 horizontal lines | ||
| Line 70: | Line 32: | ||
| * back porch: 31 horizontal lines | * back porch: 31 horizontal lines | ||
| - | so HW_LCDIF_VDCTRL1 = 542 (0x21e) | + | so HW_LCDIF_VDCTRL1 = 524 (0x20C) |
| ====== HW_LCDIF_VDCTRL0 ====== | ====== HW_LCDIF_VDCTRL0 ====== | ||
| Line 98: | Line 60: | ||
| -> 0x00340002 | -> 0x00340002 | ||
| + | |||
| + | ====== HW_LCDIF_VDCTRL3 ====== | ||
| + | by default = 0x004b0027 | ||
| + | |||
| + | * MUX_SYNC_SIGNALS = 0 | ||
| + | * VSYNC_ONLY = 1 (?) | ||
| + | * HORIZONTAL_WAIT_CNT = 48 (h back porch) + 96 (sync pulse) = 0xDE and then | ||
| + | * VERTICAL_WAIT_CNT = 31 (v back porch) + 2 (sync pulse) = 0x21 | ||
| + | |||
| + | -> 0x00DE0021 | ||
| ====== HW_LCDIF_TRANSFER_COUNT ====== | ====== HW_LCDIF_TRANSFER_COUNT ====== | ||
| Line 112: | Line 84: | ||
| DIV = 0x12 -> CLK of 21 Mhz | DIV = 0x12 -> CLK of 21 Mhz | ||
| - | Hmm, guess our chip isnt running at 454? Or is it our scope? Try 0x0F for 25MHz | + | Hmm, guess our chip isnt running at 454? Or is it our scope? Try 0x0F for 25MHz which matches with eveything else. Which means we're running at 375MHz? |
| ===== Results? ===== | ===== Results? ===== | ||
| + | PIXCLK = 0x0F | ||
| + | |||
| + | HSync = 31.3Khz (should be 31.46) | ||
| - | HSync = 31.4Khz (should be 31.46) | + | Vsync = 59.75 Hz (should be 60.04) |
| - | Vsync = 58 Hz (should be 60.04) | + | Vsync negative pulse = 63.9 uS (should be 63.57) (it is low from the negative edge of one HSync to another negative Hsync edge) |
| - | Vsync negative pulse = 63.7 uS (should be 63.57) (it is low from the negative edge of one HSync to another negative Hsync edge) | + | Hsync negative pulse = 3.83 uS (should be 3.81) |
| - | Hsync negative pulse = 4.34 uS (should be 3.81) | + | HSync Back porch = 5 uS (should be 1.9?), Hsync front porch = ~14.2uS (should be 0.9?) |
/home/ladyada/public_html/wiki/data/attic/chumbyhackerboard/vga.1285045364.txt.gz · Last modified: 2016/01/28 18:05 (external edit)
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