chumbyhackerboard:vga
Differences
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| Both sides previous revision Previous revision Next revision | Previous revision | ||
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chumbyhackerboard:vga [2010/09/21 05:04] ladyada |
chumbyhackerboard:vga [2016/01/28 18:05] (current) |
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| Line 19: | Line 19: | ||
| SO! | SO! | ||
| - | HW_LCDIF_VDCTRL2 = (96) << 24 | (640 + 16 + 48) = 0x600002C0 | + | HW_LCDIF_VDCTRL2 = (96) << 24 | (640 + 16 + 96+ 48) = 0x60000320 |
| ====== Vsync HW_LCDIF_VDCTRL1 ====== | ====== Vsync HW_LCDIF_VDCTRL1 ====== | ||
| For the LCD, this is by default = 0x0000011a (dec. 282) | For the LCD, this is by default = 0x0000011a (dec. 282) | ||
| + | |||
| + | We want... | ||
| * Per vertical line: 480 horizontal lines | * Per vertical line: 480 horizontal lines | ||
| Line 30: | Line 32: | ||
| * back porch: 31 horizontal lines | * back porch: 31 horizontal lines | ||
| - | so HW_LCDIF_VDCTRL1 = 542 (0x21e) | + | so HW_LCDIF_VDCTRL1 = 524 (0x20C) |
| ====== HW_LCDIF_VDCTRL0 ====== | ====== HW_LCDIF_VDCTRL0 ====== | ||
| Line 58: | Line 60: | ||
| -> 0x00340002 | -> 0x00340002 | ||
| + | |||
| + | ====== HW_LCDIF_VDCTRL3 ====== | ||
| + | by default = 0x004b0027 | ||
| + | |||
| + | * MUX_SYNC_SIGNALS = 0 | ||
| + | * VSYNC_ONLY = 1 (?) | ||
| + | * HORIZONTAL_WAIT_CNT = 48 (h back porch) + 96 (sync pulse) = 0xDE and then | ||
| + | * VERTICAL_WAIT_CNT = 31 (v back porch) + 2 (sync pulse) = 0x21 | ||
| + | |||
| + | -> 0x00DE0021 | ||
| ====== HW_LCDIF_TRANSFER_COUNT ====== | ====== HW_LCDIF_TRANSFER_COUNT ====== | ||
| Line 72: | Line 84: | ||
| DIV = 0x12 -> CLK of 21 Mhz | DIV = 0x12 -> CLK of 21 Mhz | ||
| - | Hmm, guess our chip isnt running at 454? Or is it our scope? Try 0x0F for 25MHz | + | Hmm, guess our chip isnt running at 454? Or is it our scope? Try 0x0F for 25MHz which matches with eveything else. Which means we're running at 375MHz? |
| ===== Results? ===== | ===== Results? ===== | ||
| + | PIXCLK = 0x0F | ||
| + | |||
| + | HSync = 31.3Khz (should be 31.46) | ||
| - | HSync = 31.4Khz (should be 31.46) | + | Vsync = 59.75 Hz (should be 60.04) |
| - | Vsync = 58 Hz (should be 60.04) | + | Vsync negative pulse = 63.9 uS (should be 63.57) (it is low from the negative edge of one HSync to another negative Hsync edge) |
| - | Vsync negative pulse = 63.7 uS (should be 63.57) (it is low from the negative edge of one HSync to another negative Hsync edge) | + | Hsync negative pulse = 3.83 uS (should be 3.81) |
| - | Hsync negative pulse = 4.34 uS (should be 3.81) | + | HSync Back porch = 5 uS (should be 1.9?), Hsync front porch = ~14.2uS (should be 0.9?) |
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